Brian Chin

I also heard something about thinking that at full scale, gate-all-around could be something like 300,000 wafer per month

what's your view on pacing here and whether this could cause these investments perhaps to spread out over a longer horizon

I think you previously disclosed that $549 million reduction in backlog for the fiscal year in a filing

ASML earlier today was upbeat on its outlook for AI-driven DRAM spending overall

is it reasonable that China could go below 30% in '25 if areas like leading-edge foundry or DRAM improve

How much of your continued optimism on market and KLA growth in packaging next year involves expansion opportunities in HBM packaging?

how much of that second half outlook is tied to new cleanroom space availability

your near-term opportunity set in advanced packaging was particularly in 2.5D or CoWoS packaging rather than in HBM. Is that the case?

can you comment on the magnitude of residual spending you still see with them besides R&D and technology development?

how about the process control intensity going from 2 nanometer [indiscernible] around to 16A?

Of the $8 billion in WFE spending, on a kind of rough cut, could you partition that across on a percentage basis, advanced logic, DRAM and NAND?

is that for a 400-layer application?

For trying to resist deposition in development, can you remind us of the SAM or maybe revenue potential

Does this shipment mix actually closely match your internal production mix? Meaning that it's not just you're holding back inventory, but structurally, you've shifted a high majority of your DRAM p...

Do you expect maybe some of these other suppliers to follow more quickly this time, similar actions or lag like they did previously?

Is that an example of your test platform outperforming their internal tester?

I was wondering if you could outline maybe a few catalysts for GPU share gain over the next few years in terms of Teradyne's platform differentiation

can you give us a sense of how significantly weighted that was the second half and maybe 4Q this year

In Industrial Robotics, do you expect Q4 to ship some positive seasonality Q-on-Q?

how are you sizing the overall compute TAM this year and also a subsegment of that, the VIP SAM

When you size the VIP TAM at around $600 million in '26 and potentially $800 million in 2028, were you including SLT?

are you anticipating more meaningful advanced back-end test and packaging lines to be onshored here in the states?

can you decompose sort of how that $4.9 billion TAM for 2025 breaks down across Compute, Mobile, et cetera

can you give us maybe a better sense of where Semiconductor Test cell utilization rates are now versus a year ago

Would you mind unpacking a little bit what you mean by consolidating the go-to-market?